Redistribution layers (RDLs) are typically made of copper or a stack of several metals like a copper layer, a nickel layer on it and a cover layer of gold. These RDLs are used to reroute bond pads on a semiconductor chip, e.g., from a center row to landing pads on the rim of the semiconductor chip. Another example for RDLs is the electrical connection of bond pads on a semiconductor chip with contact pads on compliant elements mounted on the chip.
U.S. Pat. No. 6,664,176 B2, which is incorporated herein by reference, describes a method of generating a pad-rerouting for wafer level packaging, especially for chip size packaging. The method includes forming a flat contact layer on a semiconductor die. Another example of a metal RDL having solderable pads is known from Canadian Patent No. 2,388,926 A1, which is incorporated herein by reference. In this document a flat RDL, made of a stack of metals, is described.
A similar metal RDL is described in European Patent No. 1 351 294 A2, which is incorporated herein by reference. The metal RDL is formed during the last metal layer deposition of the semiconductor circuit before the final passivation is applied. The last metal layer provides structures for solder bump pads that are used for flip chip interconnection. The metal RDL can be a flat layer deposited over the next to last metal layer through an opening in dielectric layer. A final passivation layer is deposited to ensure product reliability.
It is well known that the clock frequency of semiconductors like processors or memories is increased stepwise to higher frequency ranges. At those frequencies, metal leads (such as wire bonds, etc.), which are positioned side by side or one over another, have the characteristic of capacitors.
The parasitic capacitance of current redistribution layers per length unit is estimated with the parallel plate capacitor model and has a value of about 3.5 pF. FIG. 1 illustrates a schematic cross section of a current design with a processed silicon chip 11, a first polymer layer 12 on its top surface and a metallization 13 covered by a second polymer layer 14. In the second polymer layer 14, RDL microstrips 15, 16 are embedded. Between the RDL microstrips 15, 16 and the metallization 13 a small distance is held by the second polymer layer 14.
The general equation for the capacitance is:C=ε0*εr*A/d  (1)                d=distance between plates        A=surface area        ε=dielectric constant        
The capacitance of the current design is:C1=ε0*εr*40 μm*U/5 μm  (2)C2=ε0*εr*10 μm*U/40 μm  (3)Ctot=C1+C2=(8+¼)*ε0*εr*U  (4)
These equations are based on the following assumptions:
Width of the RDL:40μmDistance between the RDL:40μmThickness of RDL:10μmDistance from RDL to Metal 2:5μm
Therefore, the critical frequency of an RDL is dominated by its parasitic capacitance. Next and future chip generations require higher critical frequencies but this can most likely not be achieved with today's design of RDLs.